View TDA9108_1067797.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

TDA9108
MONITOR HORIZONTAL PROCESSOR
. . . . . . . . .
POS/NEG SYNC INPUT SYNC POLARITY DETECTION 2 PLLs CONCEPT 2 COMPLEMENTARY OUTPUTS DC ADJUSTABLE FREQUENCY DC ADJUSTABLE DUTY CYCLE X-RAY PROT INPUT BACK PORCH CLAMPING PULSE GENERATOR H-DRIVE INHIBITION WHEN VS < VS START
DIP14 (Plastic Package)
DESCRIPTION The TDA9108 is a horizontal deflection processor specially designed for monitor applications. The H-drive output duty cycle, the horizontal frequency and the horizontal position are DC adjustable ; it accepts both POS/NEG polarity on sync input and delivers polarity information on a dedicated pin. All these features make the device a good choice for multifrequency application.In addition to this, X-ray protection, 2 complementary H-drive output , and a back porch clamping pulse generator are also included. It is a monolithic integrated circuit encapsulated in a 14 lead dual line plastic package. PIN CONNECTIONS
ORDER CODE : TDA9108
SU PP LY VOLTAGE NEGATIVE H-DRIVE
1 2 3 4 5 6 7
14 13
GR OUN D H-FREQUENCY SETTING
POSITIVE H-DRIVE DUTY CYCLE ADJUSTMENT 2nd PLL LOOP FILTER
FLYBACK INPUT BACK PORCH CLAMPING PULSE OUTPUT
12
11 10
9 8
H-OSCILLATOR CAPACITOR 1st PLL LOOP FILTER SYNC POLARITY
SYN C INPUT X-RAY PROTECTION INPUT
9108-01.EPS
October 1993
1/9
TDA9108
BLOCK DIAGRAM
HOR IZONTAL FLYBACK IN LOOP FILTER
7
6
5
SUPPLY 1
BACK PORCH CLAMP PULSE GENERATOR
2nd PHASE COMPARATOR
HORIZONTAL PULSE SHAPER
4
HORIZONTAL DUTY CYCLE
GROUND 14
INPUT 9
SYNC EXTRACTOR
H-Sync
OUTPUT STAGE
2 NEGATIVE OUTPUT 3 POSIT IVE OUTPUT
SYNC 10 POLARITY
POLARITY DETECTION
1st PHASE COMPARATOR
OSCILLATOR
THYRISTOR FUNCTION
8 X-RAY PROT INPUT
9108-02.EPS
11
LOOP FILTER
13
R
12
C
ABSOLUTE MAXIMUM RATINGS
Symbol VS V2 V4 V8 V9 V10 I2 I3 I6 I7 Ptot Tstg , Tj Supply Voltage (Pin 1) Voltage at Pin 2 Voltage at Pin 4 Voltage at Pin 8 Voltage at Pin 9 Voltage at Pin 10 Pin 2 Peak Current Pin 3 Peak Current Pin 6 Input Current Pin 7 Input Current Total Power Dissipation at Tamb 70 C Storage and Junction Temperature
o
Parameter
Value 15 18 0, VS 0 , VS 0 , VS 0, VS 1 0.5 30 10 0.9 - 40 , + 150
Unit V V V V V V A A mA W
o
9108-01.TBL 9108-03.TBL 9108-02.TBL
mA C
THERMAL DATA
Symbol R th (j-a) Parameter Thermal Resistance Junction-ambient Max. Value 90 Unit
o
C/W
ELECTRICAL CHARACTERISTICS (refer to the test circuit, VS = 12V, TA = 25oC, unless otherwise specified)
Symbol VS IS VS Parameter Supply Voltage Range Supply Current (Pin 1) Supply voltage at which the output pulses (at Pin 2 and 3) are switched off I3 = 0 Test conditions Min. 10 Typ. 12 38 Max. 13.2 55 4 Unit V mA V
2/9
TDA9108
ELECTRICAL CHARACTERISTICS (continued) (refer to the test circuit, VS = 12V, TA = 25oC, unless otherwise specified)
Symbol V9SW I9SW Parameter Sync Input Threshold Sync Input Current Test conditions Sync high Sync Low q Sync high q Sync Low
q q
Min. 2
Typ.
Max. VS 0.8 1
Unit V V A A V
HORIZONTAL SYNC. INPUT
-20 2.3
-7 2.5 2.7
SYNC POLARITY SELECTION V10th Polarity Selection Threshold Positive sync on Pin 9 for V 10 < V10th Negative sync on Pin 9 for V10 > V10th I10 V10ZL V8th Input Current Low Impedance (2k) Threshold X-ray Prot Input Threshold Voltage (when V8 > V8th Pin 2 and 3 are inhibited until VS is switched off/on) Input Current V10 = 2V V10 = 3V (see note 1) 2.6 V8 2.5 V8 3.3 1 12 6.3 2.9 3.2 A A V V A A V mA V mA V V mA mA
X-RAY PROTECTION CIRCUIT
I8
-0.5 0.5 10 0.1 2.2 8.8 9.8 1.5 3.2 150 10.8 2.7 150 100
FLYBACK INPUT V6 I6 V2 I2 V3 I3 R3 Phase Comparator Input Threshold Input Switching Current Saturation Voltage (Pin 3 grounded) I2 = 150mA Output Current (Pin 3 grounded) V2 = 5V Output Voltage (Pin 2 connected to supply) q High level (I3 = 150mA) q Low level (I3 = 100mA) Output Current Capability q Source q Sink Output Resistance q At leading edge of output pulse q At falling edge of output pulse Horizontal Output Pulse Duty Cycle on Pin 3 (high level, line transistor off time) Voltage on Pin 4 (see note 2) Serial Equivalent Resistor on Pin 4 (see note 2) f = 31.5kHz Pin 4 not connected Pin 4 not connected Pin 4 not connected
OUTPUT PULSE
3 20
DUTY CYCLE ADJUSTMENT tp V4 R4 26 30 34 %
9108-04.TBL 9108-03.EPS
0.178 VS 0.19 VS 0.202 VS 1.7 2.3 2.9
V k
Note 1 : The voltage on the polarity detection comparator is clamped by an internal Zener diode (VZ). VPin 10 - VZ When voltage on Pin 10 reaches VZ, then IPIn 10 = . 2k Note 2 : Pin 4 internal schematic
To Duty Cyc le Adjustment
VS 2k 10 DZ 2.5V
2.3k
4
0.19 VS
9108-04.EPS
3/9
TDA9108
ELECTRICAL CHARACTERISTICS (continued) (refer to the test circuit, VS = 12V, TA = 25oC, unless otherwise specified)
Symbol tpADJ Parameter Max. Horizontal Output Duty Cycle Range V4 (function of V 4) tp = K4 (see note 3) VS Duty Cycle Adjustment Coefficient Key Pulse Output Peak Voltage (emitter follower) Low Level (outside the key pulse) Phase Relation between Trailing Edge of Key Pulse and Middle of Sync. Input Pulse Key Pulse Duration Low Level Threshold Voltage High Level Threshold Voltage Charge Current Discharge Current Reference Voltage on Pin 13 Free Running Frequency Maximum Oscillator Frequency Horizontal Jitter Frequency Control Sensitivity Frequency Change when VS Drops to 7.5V Control Voltage Range Peak Control Current Input Current (blocked Phase Detector) Permissible Delay between Output Pulse Leading Edge and Flyback Pulse Leading Edge Static Control Error 9.4 to 8.2 0.85 5 tp - tf 0.2 Test conditions f = 31.5kHz Min. Typ. 50 Max. Unit % DUTY CYCLE ADJUSTMENT (continued)
K4 V7k V7L tSK tK V12 V12 I12 I12 V13 fO fMax. Jitt. fO I13 fO V5 I5 I5 tD t tD V11 I11 f t f tO V5 tO I5 tO
1.6 I7 = 5mA f = 31.5kHz Sync width = 2s 4 1.1 1.25
1.8 5 0.2 1.5 1.7 5.4 8.2 0.6 0.3 2.9 30
2 V V s s V V mA mA V kHz kHz
KEY PULSE OUTPUT 0.5 1.9 2.15
OSCILLATOR
R13 = 10k R13 = 10k R13 = 10k C12 = 2.2nF R13 = 47k C12 = 2.2nF f = 31.5kHz R13 = 10k C12 = 2.2nF 2.6 27 66
3.2 33
5 100 -6
ns Hz A % V mA A s %
PHASE COMPARATOR During flyback pulse Outside flyback pulse
SYNC PULSE-OSCILLATOR PHASE COMPARATOR Control Voltage Range Control Peak Current Phase Lock Loop Gain Catching and Holding Range Phase Relation between Middle of Flyback Pulse and Middle of Sync. Pulse Adjustment Sensitivity Adjustment Sensitivity During Sync Pulse R11-13 = 100k See Typical Application R13 = 10k C12 = 2.2nF 4.6 to 1.4 2.3 4 700 1.1 130 50 V mA kHz s Hz s mV s A s
OVERALL PHASE RELATIONSHIP
tp tfly Note 3 : td must be (Hperiod - 0.25 - ) in order to have 5% horizontal phase adjustment range. 100 2
4/9
9108-05.TBL
TDA9108
Figure 1 : Relation Ship of Main Waveform Phases
Flyback Input Pulse
tO
tf
Sync Input Signal
Phase Comparator Driving Pulse
td Back Porch Clamping Pulse V7K t SK tK
tp Output Pulse Pin 3
Hp
100
5/9
9108-05.EPS
6/9 Flyback Input
TDA9108
47k 220nF
VCC
5 7 6
TYPICAL APPLICATION
Duty Cycle Adjustment
VCC
MONOSTABLE
1 4
LINE PULSE GENERATOR 2nd PHASE COMPARATOR
LINE PULSE DETECTION
LINE
VCC
14 2 3
Line sync input : TTL level
SYNC SEPARATOR
5
9
INHIBITION
H-Sync
VCC min.
LINE OUT STAGE
Line Output
0
or
POLARITY DETECTION
OSCILLATOR
33k
0
5
10
1st PHASE COMPARATOR
8
3V X-Ray Protection
12
10nF
11 13
THYRISTOR PROTECTION FUNCTION
4.7k
100k
2.2nF 680nF 10nF 10k 47k 22k Frequency
9108-06.EPS
TDA9108
APPLICATION INFORMATION Sync Extractor and Polarity Detection This circuit is able to handle both positive or negative TTL input signal on Pin 9. The voltage on Pin 10 drives an internal inverter providing a constant sync polarity to the 1st phase comparator. When using a RC network between Pin 9 and 10 (see Typical Application), the IC will adapt itself automatically to positive or negative sync. On an other hand, and in order to simplified the application, the Pin 10 can be connected to ground or supply (through a resistor), in this case the IC will work only with one sync polarity. 1st PLL It is composed by a phase comparator, the oscillator and an external loop filter (see Figure 2) - The phase comparator receives the H-sync signal (with positive polarity) and a signal coming from the internal current controlled oscillator. The loop is closed through an external resistor between Pin 11 and 13. - The oscillatorgenerates a sawtooth waveform on Pin 12 by charging and discharging the external capacitor. The capacitor is discharging by the current flowing Pin 13 and charged by two times this latter (see Figure 3). The sawtooth is used internally to generate all the required timings. It is possible to DC control the frequency by adding or substracting a DC current on Pin 13 (see Figure 2). Figure 2
PHASE COMPARATOR
Figure 3
VREF
13
12
Pin 12
1/3T
T
2nd Phase Locked Loop To compensate the delay introduced by the horizontal final stage, the flyback pulse (Pin 6) and the oscillator waveform (Pin 12) are compared in the 2nd phase comparator. The result of the comparison is a control current which, after it has been filtered by the external capacitor on Pin 5, is sent to a phase shifter which adequately regulates the horizontal output pulses phase. The maximum phase shift allowed is td = tp - tf where tf is the flyback duration (see Figure 4). If td > tp - tf, then the horizontal output transistor will be tunned on during flyback distroying it. Figure 4
tf
VCO
H-sync
11
13
12 td
LOOP FILTER
HORIZONTAL FLYBACK
R1
9108-07.EPS
HORIZONTAL BU OFF DRIVE P1
BU ON tp HP
9108-09.EPS
7/9
9108-08.EPS
TDA9108
X-Ray Protection Input (Pin 8) When the voltage on this pin becomes higher then 2.9V (typ.), the horizontal outputs are inhibited (Pins 2 and 3) and will remains in this condition until a reset is made on supply voltage (poweroff/power-on). tfly tp (1) Hperiod - 0.25 - td 100 2 (2) td 0.36 Hp tfly - 2s 2 H-Duty Cycle (see Figure 5) The output duty cycle is variable between 0 and 50% by varying the voltage on Pin 4. In order to maintain 5% horizontal phase adjustment possibilities the following equation must be respected.
If not, tp will decrease because of H-drive trailing edge wrong position (phase shifter saturation) If not, tp will decrease because of H-drive leading edge wrong position (phase shifter saturation)
Figure 5
VPin 13 H-drive leading edge limit HORIZONTAL DRIVE Equation (2) HORIZONTAL DRIVE BU OFF H-drive trailing edge limit Equation (1) BU OFF
HORIZONTAL FLYBACK
8/9
9108-10.EPS
TDA9108
PACKAGE MECHANICAL DATA 14 PINS - PLASTIC DIP
a1
I
b Z e3
B
e Z
L
b1
E
D
14
8
F
1
7
Dimensions a1 B b b1 D E e e3 F i L Z
Min. 0.51 1.39
Millimeters Typ.
Max. 1.65
Min. 0.020 0.055
Inches Typ.
Max. 0.065
0.5 0.25 20 8.5 2.54 15.24 7.1 5.1 3.3 1.27 2.54 0.050
0.020 0.010 0.787 0.335 0.100 0.600 0.280 0.201 0.130 0.100
DIP14.TBL
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system conforms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
9/9
PM-DIP14.EPS

▲Up To Search▲

Price & Availability of TDA9108

	To Download TDA9108 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .